Broadcom’s ‘Beast’ AI Package Explained by TechTechPotato

TechTechPotato’s host uses a rare public appearance by Broadcom (AVGO) president Charlie Kawwas to unpack a dramatic shift in AI hardware packaging. In the video, he focuses on a huge multi-die AI package Kawwas calls “the beast,” shown on stage at the Raise conference in Paris.

According to TechTechPotato, this package represents where high-end AI accelerators are heading by 2028: enormous substrates crammed with compute dies, HBM stacks, IO dies, and even on-package optics. He argues that Broadcom’s roadmap implies massive growth in backend design demand and high-bandwidth memory (HBM), with potential knock-on effects for wider DRAM pricing and availability.

The host explains that Broadcom operates primarily as a contract backend design and manufacturing services company rather than a visible consumer brand. He notes that companies like Meta Platforms (META), Google, Amazon, and “frontier model” labs can design their own architectures and interconnects, but still rely on specialists like Broadcom to turn those designs into working silicon.

TechTechPotato points to a Meta MTIA chip with a Broadcom logo as an example of Broadcom’s role behind the scenes. He adds that networking silicon like Cisco’s (CSCO) "Quad Peaks," made by MediaTek, illustrates how system companies often outsource both design and IP blocks such as high-speed SerDes, compute cores, and memory controllers.

In his view, Broadcom has become one of the largest customers of foundries like TSMC (TSM) and Samsung Electronics (SSNLF) for advanced AI hardware. He argues that the company is now expanding beyond a traditional networking customer base to serve several leading AI labs, effectively becoming a central node in the custom AI accelerator ecosystem.

TechTechPotato walks through a three-step packaging roadmap that Kawwas showed on stage, highlighting shipment targets and architectural trends.

He describes the left-hand chip as similar in size to a large Cisco networking package he owns, with a central compute die and four to six HBM stacks in a CoWoS-style configuration from TSMC. According to Kawwas, Broadcom has already shipped just over a million of these units for customers.

The middle design scales up further, with two to four large compute/IO dies and between eight and twelve HBM stacks. TechTechPotato likens this layout to AMD’s (AMD) MI455X (while noting AMD does not use Broadcom this way), and says it is also built and packaged at TSMC. Kawwas reportedly expects around 5 million of these chips to ship.

The right-hand design is the 2028 target: an XPU for AI that Broadcom internally calls the "beast." TechTechPotato says it features:

• Eight red compute dies arranged in two columns by four rows
• A second stack of purple dies beneath or above those, which he thinks could be SRAM or additional compute, effectively up to 16 compute dies
• Sixteen HBM stacks, two per compute die, around the perimeter
• Two IO dies, one at the top and one at the bottom of the package
• Cutouts along the top and bottom edges reserved for optical connectivity

Kawwas, according to the video, forecast about 15 million units of this 2028-class XPU, suggesting a huge volume ramp if it materializes.

To convey the scale difference, TechTechPotato compares the Cisco package he holds—around 3 inches by 3 inches—to what he says are typical large TSMC packages of roughly 120 by 120 millimeters. He states that Broadcom’s 2028 "beast" jumps to about 180 by 210 millimeters, far larger than packages he has seen at foundry events.

He notes that Intel (INTC) has publicly shown similarly large advanced packaging through its own packaging group, suggesting that multiple ecosystems are racing toward these extreme substrates. The host also mentions that some designs may stack compute on SRAM, others SRAM on compute, and that IO approaches could vary, from PCIe/CXL to Broadcom’s own custom scale-up fabric, which he says has gone by names like "E-Sun" or "SUE."

Beyond Broadcom, he lists competitors such as Marvell, MediaTek, Alchip, GUC, Qualcomm (QCOM), and Intel’s design services. He stresses that the limiting factor is not just design capacity but the scarcity of highly skilled engineers who can eke out small frequency or power gains through EDA optimization.

TechTechPotato flags memory, not compute, as the main industry constraint for this roadmap. He argues that there may not be enough high-bandwidth memory to support all of the projected large AI packages, especially as each 2028 "beast" design would integrate 16 HBM stacks.

He suggests that if HBM supply remains tight, the industry might need an intermediate memory technology that sits between standard DDR/LPDDR and HBM in terms of bandwidth and packaging requirements. Until such alternatives emerge, he believes both HBM capacity and advanced packaging could constrain how fast Broadcom and peers can actually ship these mega-packages.

The video implies that this scramble for HBM could spill over into broader DRAM markets. By his reasoning, as high-end AI accelerators consume more wafers and packaging capacity, the cost and availability of memory for other applications—such as PCs and servers—could be affected, potentially making conventional DRAM more expensive for end users.

Looking ahead, TechTechPotato says Kawwas claimed on stage that Broadcom is already collaborating with a customer on a 2-nanometer product, smaller than the full "beast" but still advanced. After consulting with George from Chips and Cheese, he concludes this likely refers to Fujitsu’s Monaka chip, which he describes as combining a 2 nm compute die with 5 nm SRAM dies and a central IO die.

He notes that mockups or early silicon of this Monaka design have appeared at multiple conferences, framing it as one of the first glimpses of next-generation heterogeneous 2 nm packaging. In parallel, he emphasizes that Broadcom is working with four of the five leading frontier model labs—he names OpenAI and Anthropic as examples—to co-design chips around their specific needs.

According to the host, investors and industry watchers should monitor:

• How quickly 2 nm-class packaged chips like Monaka move from demo to deployment
• Whether Broadcom’s forecast of 5 million mid-generation and 15 million 2028 "beast" packages is revised
• The pace at which optics, PCIe/CXL, and custom fabrics get integrated onto these giant substrates
• The evolution of HBM supply and any emerging memory tier between DDR/LPDDR and HBM

He concludes that, if Broadcom’s roadmap plays out, these huge multi-die packages could define AI infrastructure by 2028, with major implications for foundries, packaging houses, and memory suppliers.